Drain extended MOS device design for integrated RF PA in 28nm CMOS with optimized FoM and ESD robustness

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-02T09:05:19Z	-
dc.date.available	2023-11-02T09:05:19Z	-
dc.date.issued	2015-02	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/7046974/authors#authors	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12809	-
dc.description.abstract	This paper explores drain extended MOS (DeMOS) device design guidelines for an area scaled, ESD robust integrated radio frequency power amplifier (RF PA) for advanced system-on-chip applications in 28nm node CMOS. Simultaneous improvement of device-circuit performance and ESD robustness is discussed for the first time. By device design optimization a 45% increase in gain and 25% in power-added efficiency of RF PA at 1GHz, and 5× improvements in ESD robustness are reported experimentally.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Radio frequency	en_US
dc.subject	Logic gates	en_US
dc.subject	Electric fields	en_US
dc.subject	CMOS integrated circuits	en_US
dc.subject	Electrostatic discharges	en_US
dc.subject	Robustness	en_US
dc.title	Drain extended MOS device design for integrated RF PA in 28nm CMOS with optimized FoM and ESD robustness	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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