High Yield Polymer MEMS Process for CMOS/MEMS Integration

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-02T11:08:52Z	-
dc.date.available	2023-11-02T11:08:52Z	-
dc.date.issued	2011-02	-
dc.identifier.uri	https://link.springer.com/article/10.1557/opl.2011.58	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12826	-
dc.description.abstract	MEMS community is increasingly using SU-8 as a structural material because it is self-patternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper.	en_US
dc.language.iso	en	en_US
dc.publisher	Springer	en_US
dc.subject	EEE	en_US
dc.subject	MEMS	en_US
dc.subject	CMOS/MEMS	en_US
dc.subject	CMOS wafer	en_US
dc.title	High Yield Polymer MEMS Process for CMOS/MEMS Integration	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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