DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12842
Title: Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV technique
Authors: Rao, V. Ramgopal
Keywords: EEE
Ge pMOSFET
Interface trap
Oxide trap
Issue Date: Jun-2009
Publisher: IEEE
Abstract: The interface trap density of fresh TiN/TaN gated HfO 2 /SiO 2 /Si/epi-Ge pMOSFETs is measured using the DCIV technique. Its temperature dependence is also discussed here. We observe a polarity dependent DCIV peak shift. The bias temperature stress induced interface trapped charge and oxide trapped charge shifts are also systematically investigated in this work.
URI: https://ieeexplore.ieee.org/document/5166133
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12842
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.