DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12843
Title: DC & transient circuit simulation methodologies for organic electronics
Authors: Rao, V. Ramgopal
Keywords: EEE
Look-up table (LUT)
Organic thin film transistor (OTFT)
Particle swarm optimization (PSO)
SEQUEL
Issue Date: 2009
Publisher: IEEE
Abstract: This work establishes a novel circuit simulation methodology for organic thin film transistors (OTFTs). Because of a lack of well developed physical models for OTFTs and due to the limitations of conventional parameter extraction techniques, the approaches presented in this work come in handy for circuit designers. The first approach uses a look-up table (LUT) model, which is implemented in a general purpose public-domain circuit simulator SEQUEL (solver for circuit equations with user-defined elements). In the second approach, circuit simulation is performed using equivalent SPICE parameters, which are extracted using a global optimization technique namely particle swarm optimization (PSO) algorithm. A good match has been observed between LUT simulations and SPICE based circuit simulations for both DC and transient cases.
URI: https://ieeexplore.ieee.org/document/5166122?arnumber=5166122
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12843
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.