DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12859
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-04T06:24:46Z-
dc.date.available2023-11-04T06:24:46Z-
dc.date.issued2006-
dc.identifier.urihttps://ieeexplore.ieee.org/document/1581430-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12859-
dc.description.abstractMOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectTutorialen_US
dc.subjectCMOS technologyen_US
dc.subjectAnalog circuitsen_US
dc.subjectCMOS analog integrated circuitsen_US
dc.subjectCMOS digital integrated circuitsen_US
dc.titleAnalog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologiesen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.