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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12859
Title: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
Authors: Rao, V. Ramgopal
Keywords: EEE
Tutorial
CMOS technology
Analog circuits
CMOS analog integrated circuits
CMOS digital integrated circuits
Issue Date: 2006
Publisher: IEEE
Abstract: MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.
URI: https://ieeexplore.ieee.org/document/1581430
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12859
Appears in Collections:Department of Electrical and Electronics Engineering

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