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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12874
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-06T09:48:58Z-
dc.date.available2023-11-06T09:48:58Z-
dc.date.issued2003-
dc.identifier.urihttps://ieeexplore.ieee.org/document/1197802-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12874-
dc.description.abstractThe effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (V/sub CG/) and is insensitive to changes in drain bias (V/sub D/) CHISEL degradation is insensitive to changes in both V/sub CG/, and V/sub D/. Furthermore, CHISEL always shows lower degradation when compared to CHE under identical bias and similar programming time. The possible physical mechanisms responsible for the above behavior are clarified by using full band Monte-Carlo simulations.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectChannel hot electron injectionen_US
dc.subjectEPROMen_US
dc.subjectDegradationen_US
dc.subjectNonvolatile memoryen_US
dc.subjectIntegrated circuit reliabilityen_US
dc.subjectEnergy Consumptionen_US
dc.subjectThreshold voltageen_US
dc.titleEffect of programming biases on the reliability of CHE and CHISEL flash EEPROMsen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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