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http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12875| Title: | The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs |
| Authors: | Rao, V. Ramgopal |
| Keywords: | EEE Reliability engineering EPROM Doping Integrated circuit technology Design engineering |
| Issue Date: | Sep-2003 |
| Publisher: | IEEE |
| Abstract: | The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design. |
| URI: | https://ieeexplore.ieee.org/document/1256933 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12875 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
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