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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-07T04:08:27Z-
dc.date.available2023-11-07T04:08:27Z-
dc.date.issued2002-
dc.identifier.urihttps://ieeexplore.ieee.org/document/1025667-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12883-
dc.description.abstractIn the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectBoronen_US
dc.subjectWireen_US
dc.subjectCMOS technologyen_US
dc.subjectGrain sizeen_US
dc.subjectCMOS processen_US
dc.subjectTungstenen_US
dc.titleSuppression of boron penetration by hot wire CVD polysiliconen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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