DSpace logo

  1. BITS Pilani Institutional Repository
  2. BITS Faculty Publications
  3. Department of Electrical and Electronics Engineering
Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12885
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-07T04:17:32Z-
dc.date.available2023-11-07T04:17:32Z-
dc.date.issued2002-09-
dc.identifier.urihttps://ieeexplore.ieee.org/abstract/document/1503933-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12885-
dc.description.abstractSingle halo (SH) MOSFETs are recently proposed for mixed signal applications in view of their superior analog performance such as gain, transconductance, output resistance etc [1]. In this work, we investigate the hot carrier degradation behaviour of SH and conventional p-MOSFETs using specific stress conditions appropriate for analog applications. The degradation of analog device parameters due to Cannel Hot carrier (CHC) stress and its implications on circuit operation are discussed.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectMOSFET circuitsen_US
dc.subjectImplantsen_US
dc.subjectDegradationen_US
dc.subjectCurrent measurementen_US
dc.subjectAnalog circuitsen_US
dc.subjectStress measurementen_US
dc.subjectVoltageen_US
dc.titleOptimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliabilityen_US
dc.typeAnimationen_US
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
There are no files associated with this item.
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.