Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-07T06:36:09Z	-
dc.date.available	2023-11-07T06:36:09Z	-
dc.date.issued	2001-10	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/981564	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12888	-
dc.description.abstract	This paper presents results on the characterization of Lateral Asymmetric Channel (LAC) thin film silicon-on-insulator (SOI) MOSFETs. These devices are compared with conventional SOI MOSFETs having uniform channel doping. The measurements have been taken for a number of channel lengths, silicon film thicknesses, and tilt angles of implantation. The aspects studied include threshold voltage roll-off, kink effect, gate induced drain leakage (GIDL) and parasitic bipolar transistor action. Measurements have been supplemented by device simulations. The LAC devices show excellent characteristics, with many advantages over the conventional devices.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Los Angeles Council	en_US
dc.subject	Semiconductor films	en_US
dc.subject	Threshold voltage	en_US
dc.subject	Length measurement	en_US
dc.subject	Thickness measurement	en_US
dc.title	Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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