Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/12889Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, V. Ramgopal | - |
| dc.date.accessioned | 2023-11-07T06:40:59Z | - |
| dc.date.available | 2023-11-07T06:40:59Z | - |
| dc.date.issued | 2001 | - |
| dc.identifier.issn | 0277-786X | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12889 | - |
| dc.description.abstract | The performance of Jet Vapour Deposited (JVD) Silicon Nitride devices under high field stressing is reported in this paper. Border traps were generated when n-substrate capacitors were stressed with negative gate voltages. Also, an increase in bulk positive charges as well as interface trap density was observed. These results indicate that stressing under negative gate voltages may cause long term reliability problems in Metal-Nitride-Semiconductor (MNS) devices'. Stressing with positive gate voltage, however, does not show any significant degradation. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | SPIE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Border traps | en_US |
| dc.subject | Interface | en_US |
| dc.subject | Oxides | en_US |
| dc.subject | Radiation | en_US |
| dc.subject | Bias | en_US |
| dc.title | High Field Stressing Effects in JVD Nitride Capacitors | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Department of Electrical and Electronics Engineering | |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.