Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12893| Title: | Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering |
| Authors: | Rao, V. Ramgopal |
| Keywords: | EEE Optimization MOSFETs Molecular beam epitaxial growth Medical simulation Doping profiles Electric variables |
| Issue Date: | 2001 |
| Publisher: | IEEE |
| Abstract: | A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime. |
| URI: | https://ieeexplore.ieee.org/document/902703 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12893 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.