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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/12896
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dc.contributor.authorRao, V. Ramgopal-
dc.date.accessioned2023-11-07T09:24:00Z-
dc.date.available2023-11-07T09:24:00Z-
dc.date.issued2000-09-
dc.identifier.urihttps://ieeexplore.ieee.org/document/1503660-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12896-
dc.description.abstractDrain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron devices. For short channel devices, the oxide reliability improves drastically as drain bias increases. Device simulations showed that the vertical field distribution in the oxide is asymmetric for non-zero drain biases and this results in an asymmetric gate current distribution with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be enhanced with consequent improvement in gate oxide reliability.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectMOSFETsen_US
dc.subjectLow voltageen_US
dc.subjectLos Angeles Councilen_US
dc.subjectStressen_US
dc.subjectTemperatureen_US
dc.titleDrain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regimeen_US
dc.typeArticleen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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