Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-07T10:39:09Z	-
dc.date.available	2023-11-07T10:39:09Z	-
dc.date.issued	1999-09	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/1505464	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12903	-
dc.description.abstract	High-K gate dielectrics have been under extensive investigation for use in sub-lOOnm MOSFETs to suppress gate leakage. However, thicker gate dielectrics can result in degradation of the electrical performance due to increased fringing fields from the gate to source/drain. In this paper, the capacitance degradation resulting from this effect is analyzed and a simple technique to model this effect is presented.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Capacitance	en_US
dc.subject	Degradation	en_US
dc.subject	MOSFETs	en_US
dc.subject	Dielectrics and electrical insulation	en_US
dc.subject	High-K gate dielectrics	en_US
dc.subject	Gate leakage	en_US
dc.subject	MOS devices	en_US
dc.title	Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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