Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs

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DC Field	Value	Language
dc.contributor.author	Rao, V. Ramgopal	-
dc.date.accessioned	2023-11-08T05:31:13Z	-
dc.date.available	2023-11-08T05:31:13Z	-
dc.date.issued	1997-12	-
dc.identifier.uri	https://ieeexplore.ieee.org/document/650505	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12908	-
dc.description.abstract	In this paper we present experimental and simulation results on planar-doped-barrier MOSFETs (PDBFETs) and show the advantages that arise from the channel delta doping. Early and higher magnitude of velocity overshoot, suppression of avalanche multiplication, reduced hot-carrier problems are some of the advantages offered by PDBFETs over the conventional homogeneously doped MOSFETs in the sub 100 nm regime. Our low-temperature characterizations show clear ballistic transport in the fabricated 85 nm channel MOSFETs.	en_US
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Fabrication	en_US
dc.subject	MOSFETs	en_US
dc.subject	Molecular beam epitaxial growth	en_US
dc.subject	Doping profiles	en_US
dc.subject	Hot carriers	en_US
dc.subject	CMOS technology	en_US
dc.title	Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETs	en_US
dc.type	Article	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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