DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/14728
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMishra, Abhishek-
dc.date.accessioned2024-05-06T08:49:59Z-
dc.date.available2024-05-06T08:49:59Z-
dc.date.issued2014-07-
dc.identifier.urihttps://www.sciencedirect.com/science/article/pii/S0307904X13008147-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/14728-
dc.description.abstractEnergy efficient voltage scheduling for multi-core processors is an important issue in the context of parallel and distributed computing. Dynamic voltage scaling (DVS) is used to reduce the energy consumption of cores. Nowadays processor vendors are providing software for DVS. We consider a system using a single multi-core processor with software controlled DVS having a finite set of discretely available core speeds. Our contribution to this work is solving a well-known energy efficient voltage scheduling problem on the considered system. The problem that we consider is to find a minimum energy voltage scheduling for a given computational load that has to be completed within a given deadline. First we show that the existing methods to solve this problem on other processor models fail to apply on our processor model. Then we formulate an Integer Program (IP) for the problem.en_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.subjectComputer Scienceen_US
dc.subjectDynamic Voltage Scalingen_US
dc.subjectEnergy Efficient Schedulingen_US
dc.subjectInteger Linear Programmingen_US
dc.subjectMulti-Core Processorsen_US
dc.titleEnergy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scalingen_US
dc.typeArticleen_US
Appears in Collections:Department of Computer Science and Information Systems

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.