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Title: | Convolutional Neural Network Hardware Optimization Using Bayesian Method |
Authors: | Asati, Abhijit Shenoy, Meetha V. |
Keywords: | EEE Hyperparameters Convolutional Neural Networks Bayesian optimization algorithm CIFAR-10 |
Issue Date: | Apr-2024 |
Publisher: | IEEE |
Abstract: | Convolutional Neural Network (CNN) models have demonstrated significant benefits in the realm of computer vision and applications related to image processing. Optimizing hyperparameters in CNN models is crucial to ensuring an effective implementation of the model, whether on software, hardware, or a ‘software-hardware co-design’ platform, thereby enhancing overall performance and results. This work proposes a CNN architecture and applies the Bayesian optimization algorithm to find the best set of hyperparameter values which reduces training and recognition time both. In addition, a new parameter i.e., ‘Network optimization parameter’ (NOP) is defined which considers optimization of hardware resources for a given accuracy of the trained model. This parameter needs to be minimized which helps evaluate the best set of hyperparameter values and is essential for further implementing the CNN model in the hardware platform. The optimization is performed on both the processors, a Central Processing Unit (CPU) and a Graphical Processing Unit (GPU), in optimizing the CNN model to clearly understand the impacts of utilizing different processing units. An accuracy of 99.48 % is achieved for the Modified National Institute of Standards and Technology (MNIST) database, and an accuracy of 88.78 % is achieved for the Canadian Institute For Advanced Research (CIFAR-10) database. The proposed models are highly optimized and have lesser resource requirements (due to the lesser layer complexities and smaller filter sizes) while delivering higher accuracies compared to the available literature. Further, the calculated NOP for the proposed network is highly reduced compared to the published literature. |
URI: | https://ieeexplore.ieee.org/abstract/document/10493483/authors#authors http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/16491 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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