Efficient ASIC Implementation of Artificial Neural Network with Posit Representation of Floating-Point Numbers

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/16506

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DC Field	Value	Language
dc.contributor.author	Gupta, Anu	-
dc.contributor.author	Gupta, Rajiv	-
dc.date.accessioned	2024-11-26T11:04:45Z	-
dc.date.available	2024-11-26T11:04:45Z	-
dc.date.issued	2023-07	-
dc.identifier.uri	https://link.springer.com/chapter/10.1007/978-981-99-0483-9_5	-
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/16506	-
dc.description.abstract	This paper presents a low-power ASIC architecture of a feedforward Artificial Neural Network using Posit representation. The ASIC Posit shows 50% improvement over ASIC using IEEE 754 format in terms of Power and Silicon Area and is also 13% faster while achieving the same accuracy. The same design using the FPGA platform consumes more power than the ASIC design. The designs are done using Cadence RTL Encounter with TSMC 180 nm technology node.	en_US
dc.language.iso	en	en_US
dc.publisher	Springer	en_US
dc.subject	EEE	en_US
dc.subject	ASIC	en_US
dc.subject	Artificial neural networks (ANN)	en_US
dc.title	Efficient ASIC Implementation of Artificial Neural Network with Posit Representation of Floating-Point Numbers	en_US
dc.type	Book chapter	en_US
Appears in Collections:	Department of Electrical and Electronics Engineering

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