A High-Speed Bitwise Computation in SRAM Using Assisted Bitline Charging/Discharging

Abstract

Today’s era of nanoscale integration and lower technology nodes has yielded tremendously fast and compact processors and memories. However, the fundamental principle of VLSI architectures such as von-neumann remains intact. Hence, the bottleneck associated with them, such as restricted throughput due to frequent data movement, needs to be addressed in the era of pervasive computing consisting of extensive data-intensive applications such as AI, ML, DL. One possible solution to overcome this bottleneck is direct in-memory logic operations. Therefore, this paper aims to design a robust Compute-in-Memory SRAM (CiM-SRAM) capable of executing logical functions directly within memory in addition to normal read and write operations. This work proposes a logic-decoupled bitcell capable of computing universal logical functions like NAND/AND and NOR/OR. Further, to accelerate the computation, we utilize a bitline assist circuit that rapidly charges/discharges the bitline, thereby reducing the computational time by 20%. The proposed design has been simulated at 1 GHz frequency across all process corners using 45 nm technology and validated to demonstrate functional feasibility and significant performance improvement.