Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing

Abstract

The recent compute-in-memory (CiM) architectures are proposed as a promising solution to support Deep Neural Network and Convolutional Neural Network to solve large and complex tasks in various machine learning applications. The CiM architecture overcomes the limitation of the current Von-Neumann architecture by performing logic computations within the memory also called as in-memory computing. In most CiM, the in-memory logic operations are performed on the weights stored in memory using the inputs that are processed through bitlines or wordlines using pulse width modulated (PWM) signals. For precise operation, the applied input signals must be stable. However, one of the main challenges faced during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Addressing this challenge, in this work, we aim to mitigate the impact of one of these variations on the generated PWM signals. Therefore, in this work, we propose to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory. Further, to minimize the impact of process variations, we propose an autonomous on-chip calibration circuit that dynamically tunes the delay lines to obtain stable and process-invariant pulse width modulated signals. Our simulation results for the proposed DL demonstrate a total delay of 559 psec with a delay error of less than 2% under various process corners.