Design of In-Memory Computing Enabled SRAM Macro

Abstract

The era of nanoscale devices has resulted in tremendously fast and compact modern processing systems. The von-neumann architecture is still one of the most widely adopted architectures in these computing systems comprising separate memory and processing units. However, the growing computational requirements of emerging applications with large data set are posing a great challenge to these conventional computing systems due to constant data transfer between the two physically separate memory and computing block. The heavy data transportation between the processing core and memory results in large power consumption, especially for big-data applications. Addressing this challenge, we propose to bring processing closer to the memory. Therefore, in this work, we design an In-Memory Computing enabled SRAM macro (IMC-SRAM) which is capable of performing logical computations within memory in addition to normal memory operations. We utilize differential 9T bitcell and modified peripheral circuitry to realize boolean logic operation such as AND/NAND and OR/NOR within the memory array. The proposed design has been validated using SPICE simulations with operating frequency of 1GHz across all process corners using NCSU 45nm technology.