Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations

Abstract

In recent times, CMOS Delay Lines (DL) are rapidly gaining interest due to increased demand for high precision delay in VLSI systems. Delay lines serve as a fundamental block for a wide range of applications including Delay Locked Loops (DLL), Phase Locked Loop (PLL), ring oscillators, clock synchronizers, etc. providing precise time delays. However, one of the major challenges faced by the CMOS delay line is the deviation in delays due to process, voltage and temperature (PVT) variations. Addressing this challenge, in this work, we aim to mitigate the impact of one of these variations on the delay line. Therefore, we propose to design a programmable delay line (DL) based on a voltage-controlled buffer which is insensitive to the process variation. To achieve immunity against process variations and obtain a high precision delay value, a novel calibration technique is proposed which dynamically tunes the biasing voltage of the buffer resulting in a constant delay under all process corners. Our simulation results for the proposed DL demonstrate a total delay of 559 psec with a delay error of less than 2%.