DSpace logo

Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/1904
Full metadata record
DC FieldValueLanguage
dc.contributor.authorGurunarayanan, S.-
dc.date.accessioned2021-09-03T14:43:28Z-
dc.date.available2021-09-03T14:43:28Z-
dc.date.issued2000-01-03-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/1904-
dc.descriptionSupervisor: Dr. Chandra Shekharen_US
dc.language.isoenen_US
dc.publisherBITS Pilanien_US
dc.subjectPhysicsen_US
dc.subjectElectrostatic Discharge (ESD)en_US
dc.subjectElectrothermal Simulationen_US
dc.titleModelling of electrostatic discharge (ESD) protection circuits for CMOS ICSen_US
dc.typeThesisen_US
Appears in Collections:Department of Physics

Files in This Item:
File Description SizeFormat 
modelling-of-electrostatic-discharge-(esd)-protection-circuits-for-cmos-ics.pdf
  Restricted Access
4.31 MBAdobe PDFView/Open Request a copy


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.