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Results 21-30 of 58 (Search time: 0.003 seconds).
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Item hits:
Issue Date
Title
Author(s)
2013
Generic modified Baugh Wooley multiplier
Asati, Abhijit
2017-06
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems
Asati, Abhijit
2020-11
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications
Asati, Abhijit
;
Shekhar, Chandra
2009-05
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance
Asati, Abhijit
;
Shekhar, Chandra
2015
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
;
Asati, Abhijit
2021-07
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis
Asati, Abhijit
;
Shekhar, Chandra
2014
Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime
Gupta, Anu
;
Asati, Abhijit
2009-11
VLSI Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles
Asati, Abhijit
;
Shekhar, Chandra
2016
ROM based logic design for base-2 exponential and logarithm converter using fixed point number representation
Asati, Abhijit
2013
Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow
Asati, Abhijit
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Author
19
Gupta, Anu
17
Shekhar, Chandra
1
Shenoy, Meetha V
1
Shenoy, Meetha V.
Subject
5
High-level synthesis (HLS)
4
Iris localization
3
Clock gating
3
Han-Carlson Adder
3
iris recognition
3
Iris segmentation
3
LTSpice
3
MATLAB HDL coder
3
Power-delay product (PDP)
3
Sub-threshold
.
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Date issued
19
2020 - 2022
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2010 - 2019
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2008 - 2009