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Results 1-10 of 17 (Search time: 0.002 seconds).
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Issue DateTitleAuthor(s)
2020-11Speed optimal FPGA implementation of the encryption algorithms for telecom applicationsAsati, Abhijit; Shekhar, Chandra
2021-02Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithmAsati, Abhijit; Shekhar, Chandra
2009A high-speed, hierarchical 16×16 array of array multiplier designAsati, Abhijit; Shekhar, Chandra
2009-08A Novel Redundant Binary Number to Natural Binary Number ConverterGupta, Anu; Shekhar, Chandra; Asati, Abhijit
2020-07RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applicationsAsati, Abhijit; Shekhar, Chandra
2020-05High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applicationsAsati, Abhijit; Shekhar, Chandra
2008An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design styleAsati, Abhijit; Shekhar, Chandra
2012A Purely MUX Based High Speed Barrel Shifter VLSI Implementation Using Three Different Logic Design StylesAsati, Abhijit; Shekhar, Chandra
2020-11Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio ApplicationsAsati, Abhijit; Shekhar, Chandra
2009-05A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved PerformanceAsati, Abhijit; Shekhar, Chandra

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