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Results 1-9 of 9 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
2005-12
Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders
Gupta, Anu
;
Shekhar, Chandra
2009
A high-speed, hierarchical 16×16 array of array multiplier design
Asati, Abhijit
;
Shekhar, Chandra
2009-08
A Novel Redundant Binary Number to Natural Binary Number Converter
Gupta, Anu
;
Shekhar, Chandra
;
Asati, Abhijit
2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style
Asati, Abhijit
;
Shekhar, Chandra
2009-05
A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance
Asati, Abhijit
;
Shekhar, Chandra
2009-11
VLSI Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles
Asati, Abhijit
;
Shekhar, Chandra
2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic
Asati, Abhijit
;
Shekhar, Chandra
2009-12
Dual channel addition based FFT processor architecture for signal and image processing
Gupta, Anu
;
Shekhar, Chandra
;
Asati, Abhijit
2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
Asati, Abhijit
;
Shekhar, Chandra
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Author
7
Asati, Abhijit
3
Gupta, Anu
1
Asati, Abhijit
Subject
2
Architecture
2
CMOS logic circuits
1
Array-multipliers
1
Barrel shifter
1
Baugh-Wooley
1
Booth encoder
1
Circuit complexity
1
Circuit noise
1
Clock cycles
1
CMOS
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Date issued
6
2009
2
2008
1
2005