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Issue Date
Title
Author(s)
2009
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers
Gupta, Anu
2013
Characterization of Logical Effort for Improved Delay
Gupta, Anu
2016
Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime
Gupta, Anu
;
Asati, Abhijit
2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
Asati, Abhijit
;
Shekhar, Chandra
2020-10
TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node
Vidhyadharan, Sanjay
2021-02
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder
Vidhyadharan, Sanjay
2019-02
Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology
Vidhyadharan, Sanjay
2019-02
Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology
Vidhyadharan, Sanjay
2009
A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions
Rao, V. Ramgopal
2004-06
Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations
Rao, V. Ramgopal
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Author
10
Rao, V. Ramgopal
4
Vidhyadharan, Sanjay
3
Gupta, Anu
2
Asati, Abhijit
1
Shekhar, Chandra
Subject
3
Circuit simulation
2
45 nm CMOS technology
2
Analog circuits
2
Capacitance
2
Circuit optimization
2
CMOS process
2
MOS devices
2
MOSFET circuits
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Operational amplifiers
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3
2020 - 2022
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2010 - 2019
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2000 - 2009
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