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Issue Date
Title
Author(s)
2020
Simulations of the CNFETs using different high-k gate dielectrics
Gupta, Navneet
2013-08
Design of CNTFET-based 2-bit ternary ALU for nanoelectronics
Gupta, Anu
2014
A Novel Design of Ternary Full Adder Using CNTFETs
Gupta, Anu
2012
Performance Evalution Of CNTFET-Based Sram Cell Design
Gupta, Anu
2013
Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register
Gupta, Anu
2021-05
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM
Vidhyadharan, Sanjay
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Gupta, Anu
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Gupta, Navneet
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Vidhyadharan, Sanjay
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EEE
2
CNT
2
Ternary logic
1
45 nm CMOS technology
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Carbon nanotube (CNT)
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CMOS
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Device simulation
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Dual Edge Triggered DFF
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Gate-all-around Structure
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High-k gate dielectrics
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2013
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2021
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