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Results 1-9 of 9 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
2015
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
2015-04
Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology
Gupta, Anu
2015
Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis
Gupta, Anu
;
Asati, Abhijit
2014
Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime
Gupta, Anu
;
Asati, Abhijit
2018
Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits
Asati, Abhijit
2021-01
An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices
Vidhyadharan, Sanjay
2020-07
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
Vidhyadharan, Sanjay
2019
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
Vidhyadharan, Sanjay
2020-03
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
Vidhyadharan, Sanjay
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Author
4
Gupta, Anu
4
Vidhyadharan, Sanjay
3
Asati, Abhijit
Subject
9
EEE
4
Ternary logic
2
Han Carlson (HC)
2
Kogge stone (KS)
2
Pass transistor (PT)
2
Reverse body biasing (RBB)
2
TFET-based Schmitt
2
Transmission gate (TG)
1
45 nm CMOS technology
1
4x4 Baugh-Wooley Multiplier
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