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Issue Date	Title	Author(s)
2009	Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load	Asati, Abhijit; Shekhar, Chandra
2012	Design of a Static Current Simulator Using Device Matrix Approach	Asati, Abhijit
2019-09	Low-voltage, low-power SRAM circuits using subthreshold design technique	Asati, Abhijit; Gupta, Anu
2020	Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis	Asati, Abhijit; Shekhar, Chandra
2021-05	An Improved DVFS Circuit & Error Correction Technique	Asati, Abhijit
2021	An Improved Power Gating Technique with Data Retention and Clock Gating	Asati, Abhijit
2021-11	A Novel Method for Suitable Hyperparameter Selection in an Accurate Convolutional Neural Network Architecture	Asati, Abhijit; Shenoy, Meetha V.
2021-12	Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes	Asati, Abhijit
2021-12	Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages	Asati, Abhijit; Shekhar, Chandra
2022-05	Computational Operations and Hardware Resource Estimation in a Convolutional Neural Network Architecture	Asati, Abhijit; Shenoy, Meetha V
2022-05	Adiabatic Logic Code Converter Design at Different Sub-micron Technologies	Asati, Abhijit
2022-07	Dedicated hardware architecture for localizing iris in VW images	Asati, Abhijit; Gupta, Anu
2022-07	Retraction Note to: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications	Asati, Abhijit
2022-12	Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies	Asati, Abhijit
2012	3-D device matrix approach: A new algorithm for plotting energy band diagrams in semiconductors	Asati, Abhijit
2013	Automated HDL generation of two’s complement Dadda multiplier with Parallel Prefix Adders	Asati, Abhijit
2015	Design of ultra low power flip flops in sub-threshold region for bio-medical application in 45nm, 32nm and 22nm technologies	Asati, Abhijit
2016	Leakage Immune 9T-SRAM Cell in Sub-threshold Region	Gupta, Anu; Asati, Abhijit
2020-10	High-Level synthesis assisted design and verification framework for automotive radar processors	Asati, Abhijit; Shekhar, Chandra
2020	Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes	Asati, Abhijit