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Issue Date	Title	Author(s)
2008	A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic	Asati, Abhijit; Shekhar, Chandra
2012	Hardware software co-design using profiling and clustering	Asati, Abhijit
2016-02	A modular approach to random task graph generation	Asati, Abhijit
2013	Automated HDL Generation of Two’s Complement Wallace Multiplier With Paralle Prefix Adders	Asati, Abhijit
2015	Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis	Gupta, Anu; Asati, Abhijit
2016	ROM based logic design for base-2 exponential and logarithm converter using fixed point number representation	Asati, Abhijit
2017-06	Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems	Asati, Abhijit
2021-07	Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis	Asati, Abhijit; Shekhar, Chandra
2009-05	A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance	Asati, Abhijit; Shekhar, Chandra
2009-11	VLSI Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles	Asati, Abhijit; Shekhar, Chandra
2013	Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow	Asati, Abhijit
2020-11	Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications	Asati, Abhijit; Shekhar, Chandra
2012	A Purely MUX Based High Speed Barrel Shifter VLSI Implementation Using Three Different Logic Design Styles	Asati, Abhijit; Shekhar, Chandra
2020-07	RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications	Asati, Abhijit; Shekhar, Chandra
2014	Iris based biometric identification system	Asati, Abhijit
2020-05	High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications	Asati, Abhijit; Shekhar, Chandra
2013	Generic modified Baugh Wooley multiplier	Asati, Abhijit
2008	An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style	Asati, Abhijit; Shekhar, Chandra
2021-02	Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm	Asati, Abhijit; Shekhar, Chandra
2009	A high-speed, hierarchical 16×16 array of array multiplier design	Asati, Abhijit; Shekhar, Chandra