Collection's Items (Sorted by Submit Date in Descending order): 1801 to 1820 of 2012
| Issue Date | Title | Author(s) |
| 2013 | Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology | Gupta, Anu |
| 2012 | Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology | Gupta, Anu |
| 2011 | Novel Method To Implement High Frequency All Digital Phase-Locked Loop On FPGA | Gupta, Anu |
| 2013-12 | A comparative analysis of power and delay optimise digital logic families for high performance system design | Gupta, Anu |
| 2010 | Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab | Gupta, Anu; Chaturvedi, Nitin |
| 2009-12 | A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits | Gupta, Anu; Chaturvedi, Nitin; Asati, Abhijit |
| 2009 | A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers | Gupta, Anu |
| 2009-12 | Design of a High Performance, Low Power, Fully Differential Telescopic Cascode Amplifier using Common-Mode Feedback Circuit | Gupta, Anu |
| 2013 | An asynchronous 8-bit 5 MS/s pipelined ADC for biomedical sensor based applications | Gupta, Anu |
| 2014 | Performance evaluation of CNTFET based SRAM cell design | Gupta, Anu |
| 2012 | Asynchronous 8-bit pipelined ADC for self-triggered sensor based applications | Gupta, Anu |
| 2012 | An Efficient High Frequency and Low Power Analog Multiplier in Current Domain | Gupta, Anu |
| 2009 | Improved Implementation of CRL and SCRL Gates for Ultra Low Power | Gupta, Anu |
| 2008-07 | A novel sub-1 volt bandgap reference with all CMOS | Gupta, Anu |
| 2016 | A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-Bit Full Adder Design | Gupta, Anu |
| 2005-12 | Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders | Gupta, Anu; Shekhar, Chandra |
| 2006-07 | Automation of clock distribution network design for digital integrated circuits using divide and conquer technique | Gupta, Anu |
| 2008 | On-chip resistors can make a stable current reference | Gupta, Anu |
| 2009 | Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology | Gupta, Anu |
| 2009-12 | Dual channel addition based FFT processor architecture for signal and image processing | Gupta, Anu; Shekhar, Chandra; Asati, Abhijit |
Collection's Items (Sorted by Submit Date in Descending order): 1801 to 1820 of 2012
