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Issue Date	Title	Author(s)
2021-11	Passivation of Solution-Processed a-IGZO Thin-Film Transistor by Solution Processable Zinc Porphyrin Self-Assembled Monolayer	Rao, V. Ramgopal
2021-11	Charge Carrier Doping As Mechanism of Self-Assembled Monolayers Functionalized Electrodes in Organic Field Effect Transistors	Rao, V. Ramgopal
2022	Photoresponse of an off-stoichiometry thiol–ene–epoxy (OSTE+) polymer	Rao, V. Ramgopal
2022-12	Detection of tomato leaf curl New Delhi virus DNA using U-bent optical fiber-based LSPR probes	Rao, V. Ramgopal
2022-05	Gate voltage tunable temperature coefficient of resistance of WSe2 for thermal sensing applications	Rao, V. Ramgopal
2023-10	Understanding the Microscopic Origin of the Contact Resistance at the Polymer–Electrode Interface	Rao, V. Ramgopal
2023-10-17	Emerging synthesis and characterization techniques for hybrid polymer nanocomposites	Rao, V. Ramgopal
2014	Comments on An Efficient Method based on Self-Generating Disjoint Minimal Cut-Sets for Evaluating Reliability Measures of Interconnection Networks	Chakraborty, Suparna
2014	Subset Cut Enumeration of Flow Networks with Imperfect Nodes	Chakraborty, Suparna
2015-12	Irredundant Subset Cut Enumeration for Reliability Evaluation of Flow Networks	Chakraborty, Suparna
2020-05	On Area Coverage Reliability of Mobile Wireless Sensor Networks With Multistate Nodes	Chakraborty, Suparna
2020-01	A Monte-Carlo Markov chain approach for coverage-area reliability of mobile wireless sensor networks with multistate nodes	Chakraborty, Suparna
2020-03	Minimal Path-Based Reliability Model for Wireless Sensor Networks With Multistate Nodes	Chakraborty, Suparna
2019	Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications	Vidhyadharan, Sanjay
2019	An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices	Vidhyadharan, Sanjay
2019-02	Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology	Vidhyadharan, Sanjay
2019-02	Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology	Vidhyadharan, Sanjay
2019-06	A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications	Vidhyadharan, Sanjay
2019-11	An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications	Vidhyadharan, Sanjay
2020-03	A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder	Vidhyadharan, Sanjay