Collection's Items (Sorted by Submit Date in Descending order): 421 to 440 of 1603
Issue Date | Title | Author(s) |
2020-07 | Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC | Vidhyadharan, Sanjay |
2020-01 | Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node | Vidhyadharan, Sanjay |
2020-07 | Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices | Vidhyadharan, Sanjay |
2020-10 | An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger | Vidhyadharan, Sanjay |
2020-10 | TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node | Vidhyadharan, Sanjay |
2021-01 | An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder | Vidhyadharan, Sanjay |
2021-01 | An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices | Vidhyadharan, Sanjay |
2021-02 | CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder | Vidhyadharan, Sanjay |
2020-11 | An ultra-low-power CNFET-based improved Schmitt triggerdesign for VLSI sensor applications | Vidhyadharan, Sanjay |
2021-03 | Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications | Vidhyadharan, Sanjay |
2021-05 | A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM | Vidhyadharan, Sanjay |
2021-04 | Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs | Vidhyadharan, Sanjay |
2021-05 | Memristor–CMOS hybrid ultra-low-power high-speed multivibrators | Vidhyadharan, Sanjay |
2021 | Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications | Vidhyadharan, Sanjay |
2021-09 | CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications | Vidhyadharan, Sanjay |
2023-01 | Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator | Vidhyadharan, Sanjay |
2021-05 | PAT image reconstruction using augmented sparsity regularization with practicable tuning of regularization weight | Rejesh, Nadaparambil Aravindakshan |
2020-12 | Photo-acoustic tomographic image reconstruction from reduced data using physically inspired regularization | Rejesh, Nadaparambil Aravindakshan |
2013 | Photoacoustic and thermoacoustic signal characteristics study | Rejesh, Nadaparambil Aravindakshan |
2013 | Deconvolution-based deblurring of reconstructed images in photoacoustic/thermoacoustic tomography | Rejesh, Nadaparambil Aravindakshan |
Collection's Items (Sorted by Submit Date in Descending order): 421 to 440 of 1603