Collection's Items (Sorted by Submit Date in Descending order): 841 to 860 of 1603
Issue Date | Title | Author(s) |
2020-05 | A Comprehensive Review of the COVID-19 Pandemic and the Role of IoT, Drones, AI, Blockchain, and 5G in Managing its Impact | Chamola, Vinay |
2019 | A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications | Chaturvedi, Nitin |
2019-04 | An FPGA Based Hardware Accelerator for Classification of Handwritten Digits | Chaturvedi, Nitin |
2010 | Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation | Chaturvedi, Nitin; Gupta, Anu |
2013-02 | Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab | Chaturvedi, Nitin |
2013 | An adaptive coherence protocol with adaptive cache for multi-core architectures | Chaturvedi, Nitin |
2013 | An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core Architectures | Chaturvedi, Nitin |
2016 | An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems | Chaturvedi, Nitin |
2016 | Design of non-volatile asynchronous circuit using CMOS-FDSOI/FinFET technologies | Chaturvedi, Nitin |
2017 | Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET | Chaturvedi, Nitin |
2017 | A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design | Chaturvedi, Nitin |
2018 | Multiple Solutions for Reconfiguration to Address Partial Shading Losses in Solar Photovoltaic Arrays | Chaturvedi, Nitin |
2017 | An exploration of neuromorphic systems and related design issues/challenges in dark silicon era | Chaturvedi, Nitin |
2019 | A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination | Chaturvedi, Nitin |
2019 | Design of a Robust Logic Gate using Magnetic Tunnel Junction | Chaturvedi, Nitin |
2020 | Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array | Chaturvedi, Nitin |
2020 | Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation | Chaturvedi, Nitin |
2020 | Performance Analysis of GaN and ZnO Gate All Around Nanowire FET at sub-5nm Technology | Chaturvedi, Nitin |
2021-05 | Off-State Leakage Concern in Scaling Nanowire FETs | Chaturvedi, Nitin |
2021 | Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications | Chaturvedi, Nitin |
Collection's Items (Sorted by Submit Date in Descending order): 841 to 860 of 1603