Congestion-aware vertical link placement and application mapping onto 3-D network-on-chip architectures

Abstract

3-D Network-on-Chip (NoC) technology has emerged as a compelling solution in modern System-on-Chip (SoC) designs. This NoC technology effectively addresses the escalating need for high-performance and energy-efficient on-chip communication in various applications, including high-performance computing (HPC), graphics processing units (GPUs), and multiprocessor SoCs (MPSoCs). However, the efficient mapping of applications onto 3-D Network-on-Chips (3-D NoC) remains a complex challenge, necessitating the development of improved algorithms to address the issue. In this context, we present a novel neural mapping model with a reinforcement learning (RL) approach (NeurMap3D) to design application-specific 3-D NoC-based IC. Additionally, we propose the neural congestion-aware through-silicon vias (TSVs) placement and application mapping (NCTPAM) approach, which not only addresses application mapping but also incorporates TSVs placement and load balance across the TSVs for the specific application. In order to reduce the CPU execution time of NCTPAM algorithm, we propose incorporating a partial model parameter (θ) update mechanism. Experimental results indicate improved performance in terms of minimizing communication cost, load balancing across TSVs and energy consumption, highlighting the potential of our approach to enhance the efficiency of these synthesized network architectures.