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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/19787
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dc.contributor.authorColaco, J L Louella M M-
dc.date.accessioned2025-10-15T09:34:47Z-
dc.date.available2025-10-15T09:34:47Z-
dc.date.issued2024-
dc.identifier.urihttp://hdl.handle.net/10603/597377-
dc.descriptionUnder the Supervision of Prof. Biju K. Raveendran and co-supervision of Prof. Sasikumar Punnekkaten_US
dc.language.isoenen_US
dc.publisherBITS PILANI, Goa campusen_US
dc.subjectComputer scienceen_US
dc.subjectEnergy efficienten_US
dc.subjectCriticality systemsen_US
dc.titleDesign of energy efficient and fault tolerant schedulers for multi core mixed criticality systemsen_US
dc.typeThesisen_US
Appears in Collections:Department of Computer Science and Information Systems

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