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http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/20848Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, V. Ramgopal | - |
| dc.date.accessioned | 2026-04-02T10:17:19Z | - |
| dc.date.available | 2026-04-02T10:17:19Z | - |
| dc.date.issued | 2025-12-15 | - |
| dc.identifier.uri | https://www.financialexpress.com/business/news/shrinking-devices-expanding-possibilities/4075304/ | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/20848 | - |
| dc.description.abstract | A 3-nanometre transistor is no longer science fiction; it is inside the phone in your pocket. Yet classical silicon is gasping. The next leap will come from nanoelectronics: new materials, new device physics, and integration at atomic precision. This includes today’s scaled CMOS, powering everything from AI chips to edge devices. This is not just about making chips smaller. It is about making them smarter, cheaper, and greener. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Financial Express | en_US |
| dc.subject | Nanoelectronics | en_US |
| dc.subject | 3-Nanometre transistors | en_US |
| dc.subject | Scaled CMOS technology | en_US |
| dc.subject | Ultra-low-power IoT devices | en_US |
| dc.title | Making chips intelligent | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | BITS News | |
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