Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/4283Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kiran, D C | - |
| dc.date.accessioned | 2022-04-21T06:24:46Z | - |
| dc.date.available | 2022-04-21T06:24:46Z | - |
| dc.date.issued | 2014-01-08 | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4283 | - |
| dc.description | Supervisor: Prof. S. GURUNARAYANAN | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | BITS, Pilani | en_US |
| dc.subject | Electrical & Electronics Engineering | en_US |
| dc.subject | Architecture | en_US |
| dc.title | Compiler assisted parallelization and optimization for multicore architecture | en_US |
| dc.type | Thesis | en_US |
| Appears in Collections: | Department of Electrical and Electronics Engineering | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| j thesis september 2015.pdf | Thesis | 2.8 MB | Adobe PDF | View/Open |
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