Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/4471
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sai, Phaneendra P | - |
dc.date.accessioned | 2022-04-28T07:25:49Z | - |
dc.date.available | 2022-04-28T07:25:49Z | - |
dc.date.issued | 2017 | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4471 | - |
dc.description | Supervisor: M. B. Srinivas | en_US |
dc.language.iso | en | en_US |
dc.publisher | BITS, Pilani | en_US |
dc.subject | Electrical & Electronics Engineering | en_US |
dc.subject | Reversible Logic Circuits | en_US |
dc.title | Towards Realizing Low Quantum Cost Reversible Logic Circuits | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
thesis.pdf | Thesis | 1.1 MB | Adobe PDF | View/Open |
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