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  1. BITS Pilani Institutional Repository
  2. BITS Theses
  3. Department of Computer Science and Information Systems
Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/4503
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dc.contributor.authorGawali, Shubhangi-
dc.date.accessioned2022-04-29T09:23:08Z-
dc.date.available2022-04-29T09:23:08Z-
dc.date.issued2018-03-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4503-
dc.descriptionSupervisor: Biju K. Raveendran and Bharat M. Deshpandeen_US
dc.language.isoenen_US
dc.publisherBITS, Pilanien_US
dc.subjectComputer Scienceen_US
dc.subjectMulticore Hard Real Time Systemsen_US
dc.titleDesign of Energy Efficient Schedulers for Multicore Hard Real Time Systemsen_US
dc.typeThesisen_US
Appears in Collections:Department of Computer Science and Information Systems

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