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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/4559
Title: Methodologies for Area Speed and Power Optimization in High Level Synthesis for Diverse Applications
Authors: Sikka, Prateek
Keywords: Pharmacy
Power Optimization
High Level Synthesis
Diverse Applications
Issue Date: 2021
Publisher: BITS Pilani
Description: Supervisor(s): Asati, Abhijit and Shekhar, Chandra
URI: http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4559
Appears in Collections:Department of Electrical and Electronics Engineering

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02_Certificate.pdf
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03_Acknowledgement.pdf
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04_Abstract.pdf
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05_Content.pdf
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06_List of Graph and Tables.pdf
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13_Bibliography.pdf
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