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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/4559
Title: Methodologies for Area Speed and Power Optimization in High Level Synthesis for Diverse Applications
Authors: Sikka, Prateek
Keywords: Pharmacy
Power Optimization
High Level Synthesis
Diverse Applications
Issue Date: 2021
Publisher: BITS Pilani
Description: Supervisor(s): Asati, Abhijit and Shekhar, Chandra
URI: http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4559
Appears in Collections:Department of Electrical and Electronics Engineering

Files in This Item:
File Description SizeFormat 
01_Title.pdf34.23 kBAdobe PDFView/Open
02_Certificate.pdf5.08 kBAdobe PDFView/Open
03_Acknowledgement.pdf4.53 kBAdobe PDFView/Open
04_Abstract.pdf11.46 kBAdobe PDFView/Open
05_Content.pdf41.25 kBAdobe PDFView/Open
06_List of Graph and Tables.pdf29.33 kBAdobe PDFView/Open
07_Chapter 1.pdf101.15 kBAdobe PDFView/Open
08_Chapter 2.pdf225.57 kBAdobe PDFView/Open
09_Chapter 3.pdf1.09 MBAdobe PDFView/Open
10_Chapter 4.pdf4.9 MBAdobe PDFView/Open
11_Chapter 5.pdf2.89 MBAdobe PDFView/Open
12_Chapter 6.pdf35.43 kBAdobe PDFView/Open
13_Bibliography.pdf145.26 kBAdobe PDFView/Open
14_Appendix.pdf78.85 kBAdobe PDFView/Open
15_Biography.pdf306.74 kBAdobe PDFView/Open
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