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  1. BITS Pilani Institutional Repository
  2. BITS Theses
  3. Department of Electrical and Electronics Engineering
Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/4867
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dc.contributor.authorChaturvedi, Nitin-
dc.date.accessioned2022-05-14T05:51:24Z-
dc.date.available2022-05-14T05:51:24Z-
dc.date.issued2015-
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4867-
dc.descriptionSupervisor: S. Gurunarayananen_US
dc.language.isoenen_US
dc.publisherBITS Pilanien_US
dc.subjectElectronicsen_US
dc.subjectCMP Design Trendsen_US
dc.subjectMulti-Core Processorsen_US
dc.subject: Adaptive Block Migration-Replicationen_US
dc.titleTechniques to Improve the Performance of Cache Memory for Multi-Core Processorsen_US
dc.typeThesisen_US
Appears in Collections:Department of Electrical and Electronics Engineering

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