Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/4936| Title: | Optimal load shedding for power system security using pattern recognition technique |
| Authors: | Sinha, A.K. |
| Keywords: | Electronics Engineering Pattern recognition technique |
| Issue Date: | 26-Aug-1983 |
| Publisher: | BITS Pilani |
| Description: | Under Supervision: Prof. I.J. Nagrath |
| URI: | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4936 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Thesis.pdf | Thesis | 47.35 MB | Adobe PDF | View/Open |
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