Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/4936Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sinha, A.K. | - |
| dc.date.accessioned | 2022-05-25T10:32:56Z | - |
| dc.date.available | 2022-05-25T10:32:56Z | - |
| dc.date.issued | 1983-08-26 | - |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4936 | - |
| dc.description | Under Supervision: Prof. I.J. Nagrath | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | BITS Pilani | en_US |
| dc.subject | Electronics Engineering | en_US |
| dc.subject | Pattern recognition technique | en_US |
| dc.title | Optimal load shedding for power system security using pattern recognition technique | en_US |
| dc.type | Thesis | en_US |
| Appears in Collections: | Department of Electrical and Electronics Engineering | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Thesis.pdf | Thesis | 47.35 MB | Adobe PDF | View/Open |
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