Please use this identifier to cite or link to this item:
http://dspace.bits-pilani.ac.in:8080/jspui/handle/123456789/5179| Title: | High Performance Binary Logarithmic and BCD Multiplier Architectures |
| Authors: | Ahmed, Syed Ershad |
| Keywords: | Electrical & Electronics Engineering Technology |
| Issue Date: | 2017 |
| Publisher: | BITS Pilani |
| Description: | Under Supervision: Srinivas, M. B |
| URI: | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/5179 |
| Appears in Collections: | Department of Electrical and Electronics Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Thesis.pdf | Thesis | 10.43 MB | Adobe PDF | View/Open |
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