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Please use this identifier to cite or link to this item: http://dspace.bits-pilani.ac.in:8080/jspui/xmlui/handle/123456789/8955
Title: Study of ZnO/BST interface for thin-film transistor (TFT) applications
Authors: Gupta, Navneet
Kandpal, Kavindra
Shekhar, Chandra
Keywords: EEE
ZnO TFT
MIS-C
Interface trap density (Dit)
Hysteresis
SPICE Level-3
Issue Date: Apr-2021
Publisher: Elsevier
Abstract: This work presents an investigation of ZnO/BST interface for the potential use of (Ba,Sr)TiO3 as a gate–dielectric in ZnO based thin-film transistors (TFTs) for low-voltage operation. A metal-insulator-semiconductor capacitor (MIS-C) structure, which consists of a Pt/BST/ZnO stack, was fabricated on a corning glass substrate. The capacitance-voltage (C-V) characteristic of MIS-C gives the capacitance peak in both forward and backward sweep. This peak behavior of BST is due to its paraelectric nature attributed by changing the direction of a polar molecule over the applied electric field. C-V curve of ZnO/BST MIS-C structure exhibits a counter-clockwise hysteresis of -1.33 V due to the existence of donor-like oxygen vacancies present in BST and ZnO interface. The subthreshold slope of the device was found to be 203 mV/ decade and calculated using the measurement of interface state density (Dit). ZnO/BST interface also exhibits a very low value of leakage current density (3.148 × 10−7 Acm−2). Thus, the use of BST as a gate-dielectric in ZnO TFT has excellent potential, owing to its steep subthreshold slope, which implies fast switching and low off-state current.
URI: https://www.sciencedirect.com/science/article/pii/S2468023021000730
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8955
Appears in Collections:Department of Electrical and Electronics Engineering

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