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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Gupta, Navneet | - |
dc.date.accessioned | 2023-02-06T09:57:18Z | - |
dc.date.available | 2023-02-06T09:57:18Z | - |
dc.date.issued | 2014-01 | - |
dc.identifier.uri | https://jnep.sumdu.edu.ua/download/numbers/2013/4/articles/en/jnep_2013_V5_04054.pdf | - |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8999 | - |
dc.description.abstract | This work presents the effect of grain boundaries in nanocrystalline silicon thin-film transistors (nc-Si TFT). In this study, it is assumed that the nanocrystalline silicon film which is used as the channel material in TFT consists of grain boundaries perpendicular as well as parallel to the carrier flow. Analytical model for mobility due to perpendicular GBs (perp) and mobility due to parallel GBs (parallel) are developed separately and then the overall (effective) mobility, FE, is calculated incorporating both type of GBs. Thereafter the overall (effective) mobility μFE and drain current are plotted as a function of gate voltage. The trend observed from the theoretical plot of drain current versus gate voltage is in agreement with the experimentally observed trend. | en_US |
dc.language.iso | en | en_US |
dc.publisher | JOURNAL OF NANO- AND ELECTRONIC PHYSICS | en_US |
dc.subject | EEE | en_US |
dc.subject | Grain boundaries | en_US |
dc.subject | Nanocrystalline Silicon | en_US |
dc.subject | TFT | en_US |
dc.title | Modeling of Field Effect Mobility Using Grain Boundaries on Nanocrystalline Silicon Thin-Film Transistor (nc-Si TFT) | en_US |
dc.type | Article | en_US |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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