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Title: | Effect of trap states at the oxide-silicon interface in polycrystalline silicon thin-film transistors |
Authors: | Gupta, Navneet |
Keywords: | EEE Thin film transistor (TFT) Silicon Polycrystalline silicon Trap states Threshold voltage |
Issue Date: | 2008 |
Publisher: | World Scientific |
Abstract: | This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other. |
URI: | https://www.worldscientific.com/doi/abs/10.1142/S0217979208049406 http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9009 |
Appears in Collections: | Department of Electrical and Electronics Engineering |
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